Difference between revisions of "RUN 125 TP Efficiency"
Rfarinelli (talk | contribs) (Created page with "Data analyzed after the event generation. The analysis macro is written in $TER/src/event.C 88 chip analyzed and it turns out that the TP from some chip does not reach the en...") |
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88 chip analyzed and it turns out that the TP from some chip does not reach the end of the readout chain, in details: | 88 chip analyzed and it turns out that the TP from some chip does not reach the end of the readout chain, in details: | ||
| − | + | {| class="wikitable" | |
| − | Chip Efficiency Note | + | |+ |
| − | + | !Chip | |
| − | 5 0 | + | !Efficiency |
| − | 15 0% Also seen in decoded file | + | !Note |
| − | + | |- | |
| − | + | |5 | |
| − | 70 0% Also seen in decoded file | + | |0 |
| − | 82,83,86,87 0% Also seen in decoded file | + | |TFINE = 1008 always -> rejected in ana.C |
| − | + | |- | |
| − | The others TP shows an efficiency above 95%. Where the efficiency is measured as: | + | |6 |
| + | |3% | ||
| + | | | ||
| + | |- | ||
| + | |15 | ||
| + | |0% | ||
| + | |Also seen in decoded file | ||
| + | |- | ||
| + | |17 | ||
| + | |70% | ||
| + | |TD problem | ||
| + | |- | ||
| + | |70 | ||
| + | |0% | ||
| + | |Also seen in decoded file | ||
| + | |- | ||
| + | |82,83,86,87 | ||
| + | |0% | ||
| + | |Also seen in decoded file | ||
| + | |}The others TP shows an efficiency above 95%. Where the efficiency is measured as: | ||
chip_efficiency = # events with 1 TP on that chip / # total event with at least 1 TP | chip_efficiency = # events with 1 TP on that chip / # total event with at least 1 TP | ||
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The time difference between this time has been measured for each TP of the Layer and it is shown that the time efficiency (TP_Chip_i = TP_Layer) is 85-95%. If we consider at least 1 clock discrepancy (TP_Chip_i = TP_Layer +- 1 clock) then the time efficiency goes above 95% | The time difference between this time has been measured for each TP of the Layer and it is shown that the time efficiency (TP_Chip_i = TP_Layer) is 85-95%. If we consider at least 1 clock discrepancy (TP_Chip_i = TP_Layer +- 1 clock) then the time efficiency goes above 95% | ||
| − | Here are saved the results of the efficiency and time efficiency of each TP: [ | + | Here are saved the results of the efficiency and time efficiency of each TP: [https://wiki.fe.infn.it/besiii/img_auth.php/8/87/TP_test_RUN_125.txt] |
Revision as of 21:23, 25 June 2019
Data analyzed after the event generation. The analysis macro is written in $TER/src/event.C
88 chip analyzed and it turns out that the TP from some chip does not reach the end of the readout chain, in details:
| Chip | Efficiency | Note |
|---|---|---|
| 5 | 0 | TFINE = 1008 always -> rejected in ana.C |
| 6 | 3% | |
| 15 | 0% | Also seen in decoded file |
| 17 | 70% | TD problem |
| 70 | 0% | Also seen in decoded file |
| 82,83,86,87 | 0% | Also seen in decoded file |
The others TP shows an efficiency above 95%. Where the efficiency is measured as:
chip_efficiency = # events with 1 TP on that chip / # total event with at least 1 TP
A TP reference for each Layer has been measured as the mode of the TP of the layer.
The time difference between this time has been measured for each TP of the Layer and it is shown that the time efficiency (TP_Chip_i = TP_Layer) is 85-95%. If we consider at least 1 clock discrepancy (TP_Chip_i = TP_Layer +- 1 clock) then the time efficiency goes above 95%
Here are saved the results of the efficiency and time efficiency of each TP: [1]
