RUN 134 TP Efficiency

Data analyzed after the event generation. The analysis macro is written in $TER/src/event.C

88 chip analyzed and it turns out that the TP from some chip does not reach the end of the readout chain, in details:

Chip	Efficiency	Note
3	5%	blocked between ana and event (unknown)
5	0%	TFINE = 1008 always -> rejected in ana.C
15	0%	does not see TP (known)
17	70%	TD problem
40	3%	does not see TP
44,45	7%	8/10 bit error
70	0%	does not see TP (known)
82,83,86,87	0%	8/10 bit error ??

The others TP shows an efficiency above 95%. Where the efficiency is measured as:

chip_efficiency = # events with 1 TP on that chip / # total event with at least 1 TP

A TP reference for each Layer has been measured as the mode of the TP of the layer.

The time difference between this time has been measured for each TP of the Layer and it is shown that the time efficiency (TP_Chip_i = TP_Layer) is 85-95%. If we consider at least 1 clock discrepancy (TP_Chip_i = TP_Layer +- 1 clock) then the time efficiency goes above 95%

Here are saved the results of the efficiency and time efficiency of each TP: [1]